View M16C28_196370.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M16C/28 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0026-0020Z Rev.0.20 2003.11.10
1. Overview
The M16C/28 group of single-chip microcomputers is built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, office/communications/portable/industrial equipment, etc
------Table of Contents------
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.
Rev.0.20
2003.11.10
page 1 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.2 Performance Outline
Table 1.2.1 lists performance outline of M16C/28 group 80-pin device. Table 1.2.2 lists performance outline of M16C/28 group 64-pin device. Table 1.2.1. Performance outline of M16C/28 group (80-pin device) Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V) (Normal-ver./T-ver.) 100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V) (Normal-ver.) 50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105C) (V-ver.) 62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125C) (V-ver.) Memory ROM (See the product list) capacity RAM (See the product list) I/O port 71 lines Multifunction timer TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels Three-phase Motor Control Timer TimerS (Input Capture/Output Compare) : 16bit base timer x 1 channel (Input/Output x 8 channels) Serial I/O 2 channels (UART0, UART1) UART, clock synchronous 1 channel (UART2) UART, clock synchronous, I2C bus1 (option3), or IE bus2 (option3) 2 channels (SI/O3, SI/O4) Clock synchronous 1 channel (Multi-Master I2C bus1 (option3)) A-D converter 10 bits x 24 channels DMAC 2 channels (trigger: 31 sources) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 25 internal and 8 external sources, 4 software sources, 7 levels Clock generation circuit 4 circuits (These circuits contain a built-in feedback * Main clock * Sub-clock resistor and external ceramic/quartz oscillator) * Ring oscillator(main-clock oscillation stop detect function) * PLL frequency synthesizer Voltage detection circuit Present (option3) Power supply voltage VCC=3.0V to 5.5V (f(BCLK)=20MHZ) (Normal-ver.) VCC=2.7V to 5.5V (f(BCLK)=10MHZ) VCC=3.0V to 5.5V (T-ver.) VCC=4.2V to 5.5V (V-ver.) Flash memory Program/erase voltage 2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.) Number of program/erase 100 times ( Block A ,Block B : 10,000 times (option3) ) Power consumption 16mA (Vcc=5V, f(BCLK)=20MHz) 25 A (Vcc=3V, f(BCLK)=f(XCIN)=32KHz on RAM) 1.8 A (Vcc=3V, f(BCLK)=f(XCIN)=32KHz, when wait mode) 0.7 A (Vcc=3V, when stop mode) Operating ambient temperature -20 to 85C / -40 to 85C (option3) (Normal-ver.) -40 to 85C (T-ver.) -40 to 105C / -40 to 125C (V-ver.) Package 80-pin plastic mold QFP Notes: 1. I2C Bus is a registered trademark of PHILIPS. 2. IE Bus is a registered trademark of NEC. 3. If you desire this option, please so specify.
Rev.0.20
2003.11.10
page 2 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Table 1.2.2. Performance outline of M16C/28 group (64-pin device) Item Number of basic instructions Shortest instruction execution time Performance 91 instructions 50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V) (Normal-ver./T-ver.) 100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V) (Normal-ver.) 50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105C) (V-ver.) 62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125C) (V-ver.) (See the product list) (See the product list) 55 lines TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels Three-phase Motor Control Timer TimerS (Input Capture/Output Compare) : 16bit base timer x 1 channel (Input/Output x 8 channels ) 2 channels (UART0, UART1) UART, clock synchronous 1 channel (UART2) UART, clock synchronous, I2C bus1 (option3), or IE bus2 (option3) 1 channel (SI/O3) Clock synchronous 1 channel (Multi-Master I2C bus1 (option3)) 10 bits x 13 channels 2 channels (trigger: 30 sources) 15 bits x 1 (with prescaler) 24 internal and 8 external sources, 4 software sources, 7 levels 4 circuits * Main clock (These circuits contain a built-in feedback * Sub-clock resistor and external ceramic/quartz oscillator) * Ring oscillator(main-clock oscillation stop detect function) * PLL frequency synthesizer Present (option3) VCC=3.0V to 5.5V (f(BCLK)=20MHZ) (Normal-ver.) VCC=2.7V to 5.5V (f(BCLK)=10MHZ) VCC=3.0V to 5.5V (T-ver.) VCC=4.2V to 5.5V (V-ver.) 2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.) 100 times ( Block A ,Block B : 10,000 times (option3) ) 16mA (Vcc=5V, f(BCLK)=20MHz) 25 A (Vcc=3V, f(BCLK)=f(XCIN)=32KHz on RAM) 1.8 A (Vcc=3V, f(BCLK)=f(XCIN)=32KHz, when wait mode) 0.7 A (Vcc=3V, when stop mode) -20 to 85C / -40 to 85C (option3) (Normal-ver.) -40 to 85C (T-ver.) -40 to 105C / -40 to 125C (V-ver.) 64-pin plastic mold QFP
Memory ROM capacity RAM I/O port Multifunction timer
Serial I/O
A-D converter DMAC Watchdog timer Interrupt Clock generation circuit
Voltage detection circuit Power supply voltage
Flash memory Program/erase voltage Number of program/erase Power consumption
Operating ambient temperature
Package Notes: 1. I2C Bus is a registered trademark of PHILIPS. 2. IE Bus is a registered trademark of NEC. 3. If you desire this option, please so specify.
Rev.0.20
2003.11.10
page 3 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.3 Block Diagram
Figure 1.3.1 is a block diagram of the M16C/28 group, 80-pin device.
8
8
8
8
8
8
8
7
8
I/O Ports
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Internal Peripheral Functions
Timer Timer A0 (16 bits) Timer A1 (16 bits) Timer A2 (16 bits) Timer A3 (16 bits) Timer A4 (16 bits) Timer B0 (16 bits) Timer B1 (16 bits) Timer B2 (16 bits) 3-phase PWM Timer S Input Capture (8 channels) Output Compare (8 channels) A-D converter (10bits x 24 channels) DMAC (2 channels) Serial Ports U(S)ART/SIO (channel 0) U(S)ART/SIO (channel 1) U(S)ART/SIO/I 2C/IEbus (channel 2) SIO (channel 3) SIO (channel 4) Multi-master I C BUS
2
System Clock Generator Xin-Xout Xcin-Xcout PLL frequency synthesizer Ring Oscillator Watchdog Timer Low voltage detect
M16C/60 series 16-bit CPU Core
Program Counter Registers R0H R0H R1H R1H R2 R2 R3 R3 A0 A0 A1 A1 FR FB SB R0L R0L R1L R1L PC Stack Pointers ISP USP Vector Table INTB Flag Register FLG Multiplier
Memory
Flash ROM
Flash ROM
(Data Flash)
RAM
Figure 1.3.1. M16C/28 Group, 80-pin Block Diagram
Rev.0.20
2003.11.10
page 4 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Figure 1.3.2 is a block diagram of the M16C/28 group, 64-pin device.
4
3
8
4
8
8
8
4
8
I/O Ports
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Internal Peripheral Functions
Timer Timer A0 (16 bits) Timer A1 (16 bits) Timer A2 (16 bits) Timer A3 (16 bits) Timer A4 (16 bits) Timer B0 (16 bits) Timer B1 (16 bits) Timer B2 (16 bits) 3-phase PWM Timer S Input Capture (8 channels) Output Compare (8 channels) A-D converter (10bits x 13 channels) DMAC (2 channels) Low voltage detect Serial Ports U(S)ART/SIO (channel 0) U(S)ART/SIO (channel 1) U(S)ART/SIO/I2C/IEbus (channel 2) SIO (channel 3) Multi-master I2C BUS System Clock Generator Xin-Xout Xcin-Xcout PLL frequency synthesizer Ring Oscillator Watchdog Timer
M16C/60 series 16-bit CPU Core
Program Counter Registers R0H R0H R1H R1H R2 R2 R3 R3 A0 A0 A1 A1 FR FB SB R0L R0L R1L R1L PC Stack Pointers ISP USP Vector Table INTB Flag Register FLG Multiplier
Memory
Flash ROM
Flash ROM
(Data Flash)
RAM
Figure 1.3.2. M16C/28 Group, 64-pin Block Diagram
Rev.0.20
2003.11.10
page 5 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.4 Product List
Tables 1.4.1 to 1.4.3 list the M16C/28 group products and Figure 1.4.1 shows the type numbers, memory sizes and packages. Table 1.4.1. Product List (1) -Normal Version Type No. M30280F6HP M30280F8HP M30280FAHP M30281F6HP M30281F8HP M30281FAHP M30280M4-XXXHP M30280M6-XXXHP M30280M8-XXXHP M30281M4-XXXHP ROM capacity 48K + 4K byte 64K + 4K byte 96K + 4K byte 48K + 4K byte 64K + 4K byte 96K + 4K byte 32K byte 48K byte 64K byte 32K byte 48K byte 64K byte RAM capacity 4K byte 4K byte 8K byte 4K byte 4K byte 8K byte 2K byte 4K byte 4K byte 2K byte 4K byte 4K byte As of November 2003 Package type Remarks 80P6Q-A Flash ROM Version 64P6Q-A
** ** ** ** ** ** * * * *
80P6Q-A Mask ROM Version 64P6Q-A
M30281M6-XXXHP * M30281M8-XXXHP * * : under planning ** : under development
Table 1.4.2. Product List (2) -T Version Type No. M30280F6THP ** M30280F8THP ** M30280FATHP ** M30281F6THP ** M30281F8THP ** M30281FATHP ** M30280M4T-XXXHP * M30280M6T-XXXHP * M30280M8T-XXXHP * M30281M4T-XXXHP * M30281M6T-XXXHP * M30281M8T-XXXHP * * : under planning ** : under development ROM capacity 48K + 4K byte 64K + 4K byte 96K + 4K byte 48K + 4K byte 64K + 4K byte 96K + 4K byte 32K byte 48K byte 64K byte 32K byte 48K byte 64K byte RAM capacity 4K byte 4K byte 8K byte 4K byte 4K byte 8K byte 2K byte 4K byte 4K byte 2K byte 4K byte 4K byte As of November 2003 Package type Remarks 80P6Q-A Flash ROM Version (T-version) 64P6Q-A
80P6Q-A Mask ROM Version (T-version) 64P6Q-A
Rev.0.20
2003.11.10
page 6 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Table 1.4.2. Product List (3) -V Version Type No. M30280F6VHP ** M30280F8VHP ** M30280FAVHP ** M30281F6VHP ** M30281F8VHP ** M30281FAVHP ** M30280M4V-XXXHP * M30280M6V-XXXHP * M30280M8V-XXXHP * M30281M4V-XXXHP * M30281M6V-XXXHP * M30281M8V-XXXHP * * : under planning ** : under development ROM capacity 48K + 4K byte 64K + 4K byte 96K + 4K byte 48K + 4K byte 64K + 4K byte 96K + 4K byte 32K byte 48K byte 64K byte 32K byte 48K byte 64K byte RAM capacity 4K byte 4K byte 8K byte 4K byte 4K byte 8K byte 2K byte 4K byte 4K byte 2K byte 4K byte 4K byte As of November 2003 Package type Remarks 80P6Q-A Flash ROM Version (V-version) 64P6Q-A
80P6Q-A Mask ROM Version (V-version) 64P6Q-A
Type No.
M3028 0 F8THP
Package type: HP : Package 80P6Q, 64P6Q
Version (no): Normal version T : T version V : V version ROM capacity / RAM capacity: 4: (32K) bytes /2K bytes 6: (48K+4K) bytes (Note 1)/4K bytes 8: (64K+4K) bytes (Note 1)/4K bytes A: (96K+4K) bytes (Note 1)/8K bytes C: (128K+4K) bytes (Note 1,2)/12K bytes
Note 1: Only flash memory version exists in "+4K bytes" Note 2: Under planning
Memory type: M: Mask ROM version F: Flash memory version Shows pin count (The value itself has no specific meaning) M16C/28 Group M16C Family
Figure 1.4.1. Type No., Memory Size, and Package
Rev.0.20
2003.11.10
page 7 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.5 Pin Configuration
Figures 1.5.1 and 1.5.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P2 0/OUTC1 0/INPC1 0/SDA MM P1 7/INT 5/INPC1 7 /IDU P2 1/OUTC1 1/INPC1 1/SCL MM P2 2/OUTC1 2/INPC1 2 P2 3/OUTC1 3/INPC1 3 P2 4/OUTC1 4/INPC1 4 P2 5/OUTC1 5/INPC1 5 P2 6/OUTC1 6/INPC1 6 P1 5/INT 3/AD TRG /IDV P2 7/OUTC1 7/INPC1 7
P6 0/RTS 0/CTS 0
P1 6/INT 4 /IDW
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P6 2/RXD 0
P1 4
P6 1/CLK 0
P0 7/AN 07
P1 0/AN 20
P1 1/AN 21
P1 2/AN 22
P1 3/AN 23
P06/AN 06 P05/AN 05 P04/AN 04 P03/AN 03 P02/AN 02 P01/AN 01 P00/AN 00 P107/AN 7/KI 3 P106/AN 6/KI 2 P105/AN 5/KI 1 P104/AN 4/KI 0 P103/AN 3 P102/AN 2 P101/AN 1 AVss P100/AN 0 VREF AVcc P97/AN 27/S IN4 P96/AN 26/S OUT4
61 62 63 64 65 66 67 68 69 70
40 39 38 37 36 35 34 33 32 31
P6 3/TXD 0 P3 0/CLK 3 P3 1/S IN3 P3 2/S OUT3 P3 3 P3 4 P3 5 P3 6 P3 7 P6 4/RTS 1/CTS 1/CTS 0/CLKS 1 P6 5/CLK 1 P6 6/RXD 1 P6 7/TXD 1
M30280Fx-XXXHP
71 72 73 74 75 76 77 78 79 80 30 29 28 27 26 25 24 23 22 21
{
P7 0/TXD 2/SDA/TA 0OUT
/RTS 1/CTS 1 /CTS0 /CLKS 1
P7 1/RXD 2/SCL/TA 0IN/CLK 1 P7 2/CLK 2/TA 1OUT/V/RXD 1 P7 3/CTS 2/RTS 2/TA 1IN/V/TXD 1 P7 4/TA 2OUT/W P7 5/TA 2IN/W P7 6/TA 3OUT
10
12
13
14
15
16
17
18
19
P8 7/XCIN
P8 0/TA 4OUT/U
P9 2/TB 2IN
P9 1/TB 1IN
P9 0/TB 0IN
P9 5/AN 25/CLK 4
P8 4/INT 2/ZP
P8 5/NMI/SD
P8 1/TA 4IN/U
P8 6/XCOUT
P7 7/TA 3IN
Vss
XIN
Vcc
P8 3/INT 1
P9 3/AN24
P8 2/INT 0
CNVss
RESET
XOUT
20
11
1
2
3
4
5
6
7
8
9
Package: 80P6Q-A
Figure 1.5.1. Pin Configuration (Top View) of M16C/28 Group, 80-pin Package
Rev.0.20
2003.11.10
page 8 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
PIN CONFIGURATION (top view)
P20/OUTC10/INPC10/SDAMM P21/OUTC11/INPC11/SCLMM
P17/INT5/INPC17 /IDU
P22/OUTC12/INPC12
P23/OUTC13/INPC13
P26/OUTC16/INPC16
P24/OUTC14/INPC14
P15/INT3/ADTRG /IDV
P25/OUTC15/INPC15
P27/OUTC17/INPC17
P60/RTS0/CTS0
P16/INT4 /IDW
P62/RXD0
34
P03/AN03
40
39
38
37
36
35
48
47
46
45
44
43
42
P02/AN02 P01/AN01 P0 /AN00 P107/AN7/KI3 P106/AN6/KI2 P105/AN5/KI1 P104/AN4/KI0 P103/AN3 P102/AN2 P101/AN1 AVss P100/AN0 VREF AVcc P93/AN24 P92/TB2IN
0
41
33
P63/TXD0
P61/CLK0
49 50 51 52 53 54 55 56
32 31 30 29 28 27 26 25
P30/CLK3 P31/SIN3 P32/SOUT3 P33 P64/RTS1/CTS1 /CTS0/CLKS1 P65/CLK1 P66/RXD1 P67/TXD1
M30281Fx-XXXHP
57 58 59 60 61 62 63 64 24 23 22 21 20 19 18 17
{
P70/TXD2/SDA/TA 0OUT /RTS1/CTS1 /CTS0 /CLKS1
P71/RXD2/SCL/TA 0IN /CLK1 P72/CLK2/TA 1OUT /V/RXD1 P73/CTS2/RTS2/TA 1IN /V/TXD1 P74/TA 2OUT /W P75/TA 2IN /W P76/TA 3OUT P77/TA 3IN
10
12
13
14
15
RESET
P81/TA 4IN /U
P83/INT1
P80/TA 4OUT /U
P91/TB1IN
P90/TB0IN
XIN
P85/NMI/SD
P86/XCOUT
P84/INT2/ZP
P82/INT0
CNVss
P87/XCIN
XOUT
Vss
Vcc
16
11
1
2
3
4
5
6
7
8
9
Package: 64P6Q-A
Figure 1.5.2. Pin Configuration (Top View) of M16C/28 Group, 64-pin Package
Rev.0.20
2003.11.10
page 9 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.6 Pin Description
Table 1.6.1 and 1.6.2 describes the available pins. Table 1.6.1 Pin Description(1) Pin name Signal name I/O type VCC,VSS Power supply input Function Apply 0V to the Vss pin, and the following voltage to the Vcc pin. 2.7 to 5.5V (Normal-ver.) 3.0 to 5.5V (T-ver.) 4.2 to 5.5V (V-ver.) Connect this pin to Vss. "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit input/ output. Connent a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. If XIN is not used (for external oscillator or external clock) connect XIN pin to VCC and leave XOUT pin open. This pin is a power supply input for the A-D converter. Connect this pin to VCC. This pin is a power supply input for the A-D converter. Connect this pin to VSS. This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input, a pull-up resister option can be selected for the entire group of four pins.Software can also select this port to function as A-D converter input pins. P04~P07 is not in 64 pin version. This is an 8-bit I/O port equivalent to P0. Additional software-select able secondary functions are: 1) P10 to P13 can act as A-D converter input pins; 2) P15 to P17 can be configured as external interrupt pins; 3) P15 to P17 can be configured as position-data-retain function input pins,and; 4) P15 can input a trigger for the A-D converter. P10~P14 is not in 64 pin version. This is an 8-bit I/O port equivalent to P0. Software can also select this port to perform as I/O for the Timer S (all pins), and MultiMaster I2C Bus (P20 and P21 only) This is an 8-bit I/O port equivalent to P0. P30 to P32 also function as SIO3 I/O, as selected by software. P34~P37 is not in 64 pin version. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as UART0 and UART1 I/O, as selected by software. This is an 8-bit I/O port equivalent to P0. P7 can also function as I/O for timer A0-A3, as selected by software. Additional programming options are: P70 to P73 can assume UART1 and UART2 I/O capabilities, and P72 to P75 can function as output pins for the threephase motor control timer.
____________
CNVSS RESET XIN XOUT
CNVSS Reset input Clock input Clock output
Input Input Input Output
AVCC AVSS VREF P00~P07
Analog power supply input Analog power supply input Reference Input Voltage input I/O port P0 Input/output
P10~P17
I/O port P1
Input/output
P20~P27
I/O port P2
Input/output
P30~P37 P60~P67 P70~P77
I/O port P3 I/O port P6 I/O port P7
Input/output Input/output Input/output
Rev.0.20
2003.11.10
page 10 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Table 1.6.2 Pin Description(2) Pin name Signal name I/O type P80~P87 I/O port P8 Input/output
P90~P93, P95~P97
I/O port P9
Input/output
Function This is an 8-bit I/O port equivalent to P0. Additional software-select able secondary functions are: 1) P80 and P81 can act as either I/O for Timer A4, or as output pins for the three-phase motor control timer; 2) P82 to P84 can be configured as external interrupt pins. P84 can be used for Timer A Zphase function; 3) P85 can be used _______ _____ as NMI/SD. P85 can not be used as I/O port while the three-phase motor control is enabled. Apply a stable "H" to P85 after setting the direction register for P85 to "0" when the three-phase motor control is enabled, and; 4) P86 and P87 can serve as I/O pins for the sub-clock generation circuit. In this latter case, a quartz oscillator must be connented between P86 (XCOUT pin) and P87 (XCIN pin). This is an 7-bit I/O port equivalent to P0. Additional software-select able secondary functions are: 1) P90 to P92 can act as Timer B0~B2 input pins; 2) P93, P95 to P97 can act as A-D converter input pins, and; 3) P96 to P97 can assume SI/O4 I/O. P95 to P97 is not in 64 pin version. This is an 8-bit I/O port equivalent to P0. This port can also function as A-D converter input pins, as selected by software. Furthermore, P104-P107 can also function as input pins for the key input interrupt function.
P100~P107 I/O port P10
Input/output
Rev.0.20
2003.11.10
page 11 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
2. Central Processing Unit(CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2 R3
R0H(R0's high bits) R0L(R0's low bits) R1H(R1's high bits)R1L(R1's low bits) R2 R3 A0 A1 FB Address registers (Note) Frame base registers (Note)
b0
Data registers (Note)
b19
b15
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19 b0
PC
b15 b0
Program counter
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OB SZ DC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are the same as R0. The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers. R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32bit data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.0.20
2003.11.10
page 12 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
2. Central Processing Unit(CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status. 2.8.1 Carry Flag (C Flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 Debug Flag (D Flag) The D flag is used exclusively for debugging purpose. During normal use, it must be set to "0". 2.8.3 Zero Flag (Z Flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, it is "0". 2.8.4 Sign Flag (S Flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, it is "0". 2.8.5 Register Bank Select Flag (B Flag) Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". 2.8.6 Overflow Flag (O Flag) This flag is set to "1" when the operation resulted in an overflow; otherwise, it is "0". 2.8.7 Interrupt Enable Flag (I Flag) This flag enables a maskable interrupt. Maskable interrupts are disabled when the I flag is "0", and are enabled when the I flag is "1". The I flag is cleared to "0" when the interrupt request is accepted. 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is "0"; USP is selected when the U flag is "1". The U flag is cleared to "0" when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than IPL, the interrupt is enabled. 2.8.10 Reserved Area When write to this bit, write "0". When read, its content is indeterminate.
Rev.0.20
2003.11.10
page 13 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
3. Memory
3. Memory
Figure 3.1 is a memory map of the M16C/28 group. The linear address space of 1M bytes extends from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30280F8HP,there are 64 Kbytes of internal ROM from F000016 to FFFFF16. The vector table for fixed interrupts, such as Reset and NMI, is mapped from FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts,etc.,can be set as desired using the interrupt table register(INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30280F8HP, 4K bytes of internal RAM is mapped to the space from 0040016 to 013FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. These devices also contain two blocks of Flash ROM as Data Flash memory to store data. These two blocks of 2K bytes are located from 0F00016 to 0FFFF16 on all versions. The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is allocated to the address from FFE0016 to FFFDB16. This vector is used by the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software Manual".
Internal RAM area Memory size 2K byte 4K byte 0000016 SFR area 0040016 Internal RAM area FFE0016 XXXXX16 RESERVED 0F00016 0FFFF16 Internal ROM area (data area) (Note1) FFFDC16 RESERVED Special page vector table 8K byte XXXXX16 00BFF16 013FF16 023FF16
Internal ROM area Memory size 32K byte 48K byte 64K byte 96K byte 128K byte
(Note2)
YYYYY16 F800016 F400016 F000016 E800016 E000016
Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer DBC NMI Reset
YYYYY16 Internal ROM area (program area) FFFFF16 FFFFF16
Note 1 : The block A (2K bytes) and block B (2K bytes) are shown (only flash memory) Note 2 : Under planning
Figure 3.1. Memory Map
Rev.0.20
2003.11.10
page 14 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
4. Special Function Register (SFR) Map
Address
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Register Name
Acronym
Value after Reset
Processor mode register 0 Processor mode register 1 System clock control register 0 System clock control register 1 Address match interrupt enable register Protect register Oscillation stop detection register Watchdog timer start register Watchdog timer control register Address match interrupt register 0 (Note 2)
PM0 PM1 CM0 CM1 AIER PRCR CM2 WDTS WDC RMAD0
0016 000010002 010010002 001000002 XXXXXX002 XX0000002 0X0000102 ??16 00??????2(Note 3) 0016 0016 X016 0016 0016 X016
Address match interrupt register 1
RMAD1
Voltage detection register 1 Voltage detection register 2 PLL control register 0 Processor mode register 2 Voltage down detection interrupt register DMA0 source pointer
(Note 4) (Note 4)
VCR1 VCR2 PLC0 PM2 D4INT SAR0
000010002 0016 0001X0102 XXX000002 0016 ??16 ??16 X?16 ??16 ??16 X?16 ??16 ??16
DMA0 destination pointer
DAR0
DMA0 transfer counter
TCR0
DMA0 control register
DM0CON
00000?002
DMA1 source pointer
SAR1
??16 ??16 X?16 ??16 ??16 X?16 ??16 ??16
DMA1 destination pointer
DAR1
DMA1 transfer counter
TCR1
DMA1 control register
DM1CON
00000?002
Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset. Note 3: Tjhe WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program. It is set to "0" when the input voltage at the Vcc pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to "1"(RAM retention limit detection circuit enable). Note 4: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset. X : Noting is mapped to this bit ? : Value indeterminate at reset
Figure 4.1. SFR Map (1 of 7)
Rev.0.20 2003.11.10 page 15 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Address
004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416 005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16 005F16 006016 006116 006216 006316 006416 006516 006616 006716 006816 006916 006A16 006B16 006C16 006D16 006E16 006F16 007016 007116 007216 007316 007416 007516 007616 007716 007816 007916 007A16 007B16 007C16 007D16 007E16 007F16
Register Name
Acronym
Value after Reset
INT3 interrupt control register IC/OC interrupt control register IC/OC interrupt control register 1, I2C-BUS interface interrupt control register IC/OC interrupt control register 2, SCLSDA interrupt control register SI/O4 interrupt control register, INT5 interrupt control register SI/O3 interrupt control register, INT4 interrupt control register UART2 Bus collision detection interrupt control register DMA0 interrupt control register DMA1 interrupt control register Key input interrupt control register A-D conversion interrupt control register UART2 transmit interrupt control register UART2 receive interrupt control register UART0 transmit interrupt control register UART0 receive interrupt control register UART1 transmit interrupt control register UART1 receive interrupt control register Timer A0 interrupt control register Timer A1 interrupt control register Timer A2 interrupt control register Timer A3 interrupt control register Timer A4 interrupt control register Timer B0 interrupt control register Timer B1 interrupt control register Timer B2 interrupt control register INT0 interrupt control register INT1 interrupt control register INT2 interrupt control register
INT3IC ICOCIC ICOC1IC, IICIC
ICOC2IC, SCLDAIC
S4IC, INT5IC S3IC, INT4IC BCNIC DM0IC DM1IC KUPIC ADIC S2TIC S2RIC S0TIC S0RIC S1TIC S1RIC TA0IC TA1IC TA2IC TA3IC TA4IC TB0IC TB1IC TB2IC INT0IC INT1IC INT2IC
XX00?0002 XXXX?0002 XXXX?0002 XXXX?0002 XX00?0002 XX00?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XXXX?0002 XX00?0002 XX00?0002 XX00?0002
Note 1: The blank areas are reserved and cannot be accessed by users. X : Noting is mapped to this bit ? : Value indeterminate at reset
Figure 4.2. SFR Map (2 of 7)
Rev.0.20 2003.11.10 page 16 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Address
008016 008116 008216 008316 008416 008516 008616
Register Name
Acronym
Value after Reset
~ ~
01B016 01B116 01B216 01B316 01B416 01B516 01B616 01B716 01B816 01B916 01BA16 01BB16 01BC16 01BD16 01BE16 01BF16
~
Flash memory control register 4 Flash memory control register 1 Flash memory control register 0 (Note 2) (Note 2) (Note 2) FMR4 FMR1 FMR0 010000002 000???0?2 ??0000012
~ ~
025016 025116 025216 025316 025416 025516 025616 025716 025816 025916 025A16 025B16 025C16 025D16 025E16 025F16
~
Ring oscillator control register Pin assignment control register Peripheral clock select register
ROCR PACR PCLKR
000001012 0016 000000112
~ ~
02E016 02E116 02E216 02E316 02E416 02E516 02E616 02E716 02E816 02E916 02EA16
~
I2C0 data shift register I2C0 address register 2 2C0 address register I I2C0 control register 0 I2C0 clock control register I2C0 start/stop condition control register I2C0 control register 1 I2C0 control register 2 I2C0 status register S00 S0D02 S0D0 S1D0 S20 S2D0 S3D0 S4D0 S10 ??16 0016 0016 0016 0016 000110102 001100002 0016 0001000X2
~
02FE16 02FF16
~ ~
Note 1:The blank areas are reserved and cannot be accessed by users. Note 2:This register is included in the flash memory version.
X : Noting is mapped to this bit ? : Value indeterminate at reset
Figure 4.3. SFR Map (3 of 7)
Rev.0.20 2003.11.10 page 17 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Address
030016 030116 030216 030316 030416 030516 030616 030716 030816 030916 030A16 030B16 030C16 030D16 030E16 030F16 031016 031116 031216 031316 031416 031516 031616 031716 031816 031916 031A16 031B16 031C16 031D16 031E16 031F16 032016 032116 032216 032316 032416 032516 032616 032716 032816 032916 032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16
Register Name TM/WG register 0 TM/WG register 1 TM/WG register 2 TM/WG register 3 TM/WG register 4 TM/WG register 5 TM/WG register 6 TM/WG register 7 WG control register 0 WG control register 1 WG control register 2 WG control register 3 WG control register 4 WG control register 5 WG control register 6 WG control register 7 TM control register 0 TM control register 1 TM control register 2 TM control register 3 TM control register 4 TM control register 5 TM control register 6 TM control register 7 Base timer register Base timer control register 0 Base timer control register 1 TM prescaler register 6 TM prescaler register 7 Function enable register Function select register Base timer reset register Divider register
Acronym G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3 G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1BTRR G1DV
Value after Reset ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 0X00X0002 0X00X0002 0X00X0002 0X00X0002 0X00X0002 0X00X0002 0X00X0002 0X00X0002 0016 0016 0016 0016 0016 0016 0016 0016 ??16 ??16 0016 0016 0016 0016 0016 0016 ??16 ??16 0016
Interrupt request register 0 Interrupt enable register 0 Interrupt enable register 1
G1IR G1IE0 G1IE1
??16 0016 0016
NMI digital debounce register P17 digital debounce register
NDDR P17DDR
FF16 FF16
Note 1:The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit ? : Value indeterminate at reset
Figure 4.4. SFR Map (4 of 7)
Rev.0.20 2003.11.10 page 18 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Address
034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816 037916 037A16 037B16 037C16 037D16 037E16 037F16
Register Name
Acronym
Value after Reset
Timer A1-1 register Timer A2-1 register Timer A4-1 register Three-phase PWM control register 0 Three-phase PWM control register 1 Three-phase output buffer register 0 Three-phase output buffer register 1 Dead time timer Timer B2 interrupt occurrence frequency set counter Position-data-retain function contol register
TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2 PDRF
??16 ??16 ??16 ??16 ??16 ??16 0016 0016 0016 0016 ??16 X?16 XXXX00002
Interrupt request cause select register 2 Interrupt request cause select register SI/O3 transmit/receive register SI/O3 control register SI/O3 bit rate generator SI/O4 transmit/receive register SI/O4 control register SI/O4 bit rate generator
IFSR2A IFSR S3TRR S3C S3BRG S4TRR S4C S4BRG
00XXXXXX2(Note 2) 0016 ??16 010000002 ??16 ??16 010000002 ??16
UART2 special mode register 4 UART2 special mode register 3 UART2 special mode register 2 UART2 special mode register UART2 transmit/receive mode register UART2 bit rate generator UART2 transmit buffer register UART2 transmit/receive control register 0 UART2 transmit/receive control register 1 UART2 receive buffer register
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB
0016 000X0X0X2 X00000002 X00000002 0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2
Note 1: The blank areas are reserved and cannot be accessed by users. Note 2: Write "1" to bit 0 after reset.
X : Noting is mapped to this bit ? : Value indeterminate at reset
Figure 4.5. SFR Map (5 of 7)
Rev.0.20 2003.11.10 page 19 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Address
038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16 039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16 03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516 03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16
Register Name Count start flag Clock prescaler reset flag One-shot start flag Trigger select register Up-down flag Timer A0 register Timer A1 register Timer A2 register Timer A3 register Timer A4 register Timer B0 register Timer B1 register Timer B2 register Timer A0 mode register Timer A1 mode register Timer A2 mode register Timer A3 mode register Timer A4 mode register Timer B0 mode register Timer B1 mode register Timer B2 mode register Timer B2 special mode register UART0 transmit/receive mode register UART0 bit rate generator UART0 transmit buffer register UART0 transmit/receive control register 0 UART0 transmit/receive control register 1 UART0 receive buffer register UART1 transmit/receive mode register UART1 bit rate generator UART1 transmit buffer register UART1 transmit/receive control register 0 UART1 transmit/receive control register 1 UART1 receive buffer register UART transmit/receive control register 2
Acronym TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB UCON
Value after Reset 0016 0XXXXXXX2 0016 0016 0016 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 ??16 0016 0016 0016 0016 0016 00??00002 00?X00002 00?X00002 X00000002 0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2 0016 ??16 ????????2 XXXXXXX?2 000010002 000000102 ????????2 ?????XX?2 X00000002
DMA0 request cause select register DMA1 request cause select register
DM0SL DM1SL
0016 0016
Note 1:The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit ? : Value indeterminate at reset
Figure 4.6. SFR Map (6 of 7)
Rev.0.20 2003.11.10 page 20 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Address
03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16
Register Name A-D register 0 A-D register 1 A-D register 2 A-D register 3 A-D register 4 A-D register 5 A-D register 6 A-D register 7
Acronym AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Value after Reset ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2 ????????2 XXXXXX??2
A-D trigger control register A-D convert status register 0 A-D control register 2 A-D control register 0 A-D control register 1
ADTRGCON ADSTAT0 ADCON2 ADCON0 ADCON1
XXXX00002 00000X002 0016 00000???2 0016
Port P0 register Port P1 register Port P0 direction register Port P1 direction register Port P2 register Port P3 register Port P2 direction register Port P3 direction register
P0 P1 PD0 PD1 P2 P3 PD2 PD3
??16 ??16 0016 0016 ??16 ??16 0016 0016
Port P6 register Port P7 register Port P6 direction register Port P7 direction register Port P8 register Port P9 register Port P8 direction register Port P9 direction register Port P10 register Port P10 direction register
P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 PD10
??16 ??16 0016 0016 ??16 ???X????2 0016 000X00002 ??16 0016
Pull-up control register 0 Pull-up control register 1 03FE16 Pull-up control register 2 03FF16 Port control register Note 1:The blank areas are reserved and cannot be accessed by users.
03FC16 03FD16
PUR0 PUR1 PUR2 PCR
0016 0016 0016 0016
X : Noting is mapped to this bit ? : Value indeterminate at reset
Figure 4.7. SFR Map (7 of 7)
Rev.0.20 2003.11.10 page 21 of 23
Under development Preliminary specification Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Package
5. Package
64P6Q-A
MMP
JEDEC Code - Weight(g) - Lead Material Cu Alloy
Plastic 64pin 1010mm body LQFP
MD
e
EIAJ Package Code LQFP64-P-1010-0.50
HD D
64 49
1
48
b2
I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
16
33
17
32
A e F L1
A2
A3
A1
y
b
x y b2 I2 MD ME
x
M
L Detail F
Lp
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 9.9 10.0 10.1 9.9 10.0 10.1 - 0.5 - 11.8 12.0 12.2 11.8 12.0 12.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 - - 0.1 - 0 10 - - 0.225 1.0 - - - - 10.4 - - 10.4
HE
E
80P6Q-A
EIAJ Package Code LQFP80-P-1212-0.5 HD
MMP
JEDEC Code - Weight(g) 0.47 Lead Material Cu Alloy
c
Plastic 80pin 1212mm body LQFP
MD
e
80
61
1
60
b2
D
l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
20
41
21
40
A F e
A2
L1
A3
x y b2 I2 MD ME
x
M
y
A1
Detail F
Lp
Rev.0.20
2003.11.10
page 22 of 23
c
b
L
Dimension in Millimeters Min Nom Max - - 1.7 0.1 0.2 0 - - 1.4 0.13 0.18 0.28 0.105 0.125 0.175 11.9 12.0 12.1 11.9 12.0 12.1 - 0.5 - 13.8 14.0 14.2 13.8 14.0 14.2 0.3 0.5 0.7 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 0.1 - - 0 10 - 0.225 - - 0.9 - - - - 12.4 - - 12.4
HE
E
ME
ME
M16C/28 Group
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Rev.0.20
2003.11.10
page 23 of 23

▲Up To Search▲

Price & Availability of M16C28

	To Download M16C28 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .